Modern electronic devices often include Very Large Scale Integration (VLSI) integrated circuits. Analysis and testing of a particular VLSI design typically includes partitioning the design into a hierarchy of sub-blocks, with each sub-block described at a variety of levels of abstraction. For example, one sub-block might include a number of transistors, organized into logic gates, with the logic gates organized to perform a particular function. Using modern Electronics Design Automation (EDA) tools, this example sub-block can be examined and tested at the transistor level, the logic gate level, and/or the functional level, for example. Further, certain performance analyses combine numerous descriptions of different sub-blocks at the functional level to examine to performance of the entire chip, or, for example, yet another sub-block, examined at the logic gate level. Varying levels of abstraction in VLSI design and analysis is well-known in the art.
However, there are cases where the boundaries between sub-blocks become problematic. For example, a boundary that is desirable with respect to physical components (e.g., transistors) can cause undesirable boundaries at higher levels of abstraction. One common instance of this problem occurs with respect to channel-connected components (CCCs). Generally, a CCC is a set of transistors and nets or nodes formed by traversing the source-drain connections of transistors within the component. Frequently, a desirable transistor layout results in a CCC that spreads across one or more logical boundaries, such that the logical boundaries contain an incomplete CCC circuit.
But many EDA tools require complete circuits to provide meaningful analysis of the sub-blocks. In fact, this need for complete circuits applies to timing analysis, electromigration analysis, noise analysis, transistor level tuning, transistor level circuit checking, generation of gate equivalent logic models for transistor circuits, and other common design and analysis tasks. There are currently no satisfactory solutions to the question of how to incorporate incomplete circuits, especially CCCs, in EDA analysis, although there are some approaches that seek to work around the problem.
For example, one known technique is to repartition the design such that all the devices that make up a circuit are in the same sub-block. This approach suffers from the significant drawback that the sub-block is thus optimized for circuit completeness, which is not necessarily the optimal performance configuration, especially for VLSI designs. While this approach allows for easier analysis, the resultant circuit design may be non-optimal.
Another technique involves performing the analysis at a high enough level in the design hierarchy such that there are no incomplete circuits in the analyzed block boundary. That is, more and more components are added to the analysis block, until a preliminary assessment shows that there are no incomplete circuits in the analysis block. This technique, however, can add substantial analysis steps that far outweigh any benefit of the analysis itself. Further, in some cases the resultant block may contain so many components that it exceeds the capacity of the EDA tool to analyze the block, rendering the technique completely ineffective. Additionally, this technique makes analysis of lower abstraction levels with incomplete circuits, impossible.
Still another known technique includes estimating minimum and maximum loads at the pass transistor inputs of an incomplete CCC, as for example, in the Kumashiro approach, as described in U.S. Pat. No. 6,301,692 to Kumashiro, et al. The Kumashiro approach obtains minimum and maximum capacity values, in advance of analysis, for all the states for an input pin of each gate, and uses the capacity values to find minimum and maximum gate delay values. Given the pre-obtained gate delays, the Kumashiro analysis determines whether given timing conditions are satisfied by static timing analysis. But the Kumashiro approach suffers from, among other disadvantages, the disadvantage that it must assume independent worst-case logic states at each of the separate partial CCCs, leading to an overly pessimistic overall analysis. Further, the Kumashiro approach requires additional computation and estimation, increasing the cost and complexity of the circuit design process.
Generally, all of the known approaches follow a similar development paradigm, shown in the exemplary methodology of FIG. 1. FIG. 1 is a high-level block diagram illustrating certain components of a system 100 for circuit design and testing, in accordance with a prior art methodology. System 100 includes design tools 102, which are conventional design tools used to build a model 104 of an electronic circuit.
Design tools 102 generate circuit model 104 in a format suitable for analysis tools 106. Analysis tools 106 analyze model 104 and generate revisions 108 based on the analysis. For example, analysis tools 106 can receive a netlist-format model 104, and return revisions 108 that include “errata” and an “abstraction” describing the behavior of the circuit modeled in model 104.
The design engineer can use revisions 108 in conjunction with design tools 102 to generate a revised model 104, which is then subject to analysis, and so forth, until the circuit design process is complete. One skilled in the art will understand that this methodology is a common approach to electronic design analysis (EDA). This approach, however, suffers from the disadvantages noted above with respect to the systems that follow it.
Therefore, there is a need for a system and/or method for hierarchical analysis of electronic circuits that addresses at least some of the problems and disadvantages associated with conventional systems and methods.